1. Field of the Invention
This invention relates generally to analog-to-digital converters. More particularly, this invention relates to an analog-to-digital converter (ADC) architecture based on a finite impulse response (FIR) filter.
2. Description of the Prior Art
Modern communication and mixed signal applications require high resolution ADCs. The sigma-delta ADC has been a best candidate in data acquisition, voice CODEC and receiver paths in communications channels, since a sigma-delta ADC offers many advantages such as lower power consumption, smaller silicon area requirements, and very good immunity with respect to process non-idealities. Present hand-held applications, however, such as cellular phones, desperately require very small power consumption due to the limited battery life. The primary current consuming building block and key building block in the sigma-delta ADC is an analog amplifier. In order to make a higher speed amplifier, more current consumption and more silicon area are required.
Several rules must be considered when designing a higher order sigma-delta ADC. The order of the noise transfer function is determined by the order of the integrator, for example; and each integrator requires one amplifier. The order of the sigma-delta ADC therefore indicates the minimum number of required amplifiers.
In view of the foregoing, it is both advantageous and desirable to provide a higher order sigma-delta ADC architecture that does not require one amplifier per integrator, thereby requiring less power consumption and less silicon area.